1. Field of the Invention
This invention pertains to a signal processing architecture for an imaging system and, more particularly, to a digital processing circuit utilizing one or more line delays to process the image signals generated by a high resolution image sensor.
2. Description Relative to the Prior Art
In order to obtain quality color video images from a one-chip color charge-coupled device (CCD) sensor, a large amount of signal processing is required. FIG. 1 shows a known one-chip color CCD imaging system using custom digital video processing circuits. This system is described in detail in "A Digital Color CCD Imaging System Using Custom VLSI Circuits," by K. A. Parulski, L. J. D'Luna, and R. H. Hibbard, IEEE Trans. on Consumer Electronics, Vol. 35, No. 3, August 1989, pp. 382-388. This paper shows how the digital video processing is pipelined and operated at the same pixel rate as the image sensor, so that a framestore is not required. To minimize chip area, the signal processing has been carefully designed so that no multipliers are required.
The color imaging system shown in FIG. 1 includes a CCD sensor 10 and a color filter array 12. The color filter array 12 contains a pattern of red, green, and blue filters that provide a single red, green, or blue value for each photosite of the CCD sensor 10. The image sensor 10 is an interline transfer CCD with 570 horizontal by 484 vertical active pixels (e.g., the Model KAI-0280 sensor manufactured by the Eastman Kodak Co.) that is packaged in a leadless chip carrier which is mounted on a thick film hybrid substrate 14. The hybrid 14 includes the necessary clock drivers and bias circuits 16 and an output amplifier 18. The sensor output is processed by a clamp/sample-and-hold circuit 20 that implements a known correlated double sampling function. The processed sensor output signal is then digitized with a conventional flash A/D converter 22 and input to an interpolation processor 24.
As described in greater detail in the afore-mentioned paper, the interpolation processor 24 clamps the input video to the average sensor optical black reference value, conceals defects by substituting therefor the values of adjacent pixels, interpolates missing luminance pixels, converts to log space to perform gain control and white balance, and then interpolates chrominance values in log space. The latter interpolation is first completed in the vertical direction using on-chip line delays, and then in the horizontal direction using shift and add circuits. The log RGB outputs of the interpolation processor 24 are connected to the inputs of a post processor 26, which performs black level correction for lens flare, a 3 x 3 color matrix correction, gamma correction, and edge-enhancement. The edge enhancement improves the "crispness" of the image by extracting vertical and horizontal high frequency detail from the green channel and then adding the extracted detail back to the RGB signals. For this reason the post-processor 26 includes on-chip line delay in order to provide symmetric three-line vertical enhancement.
System timing is controlled by a programmable sequencer 28, which is described in "The EBS-1, an EPROM-based Sequencer ASIC," by M. D. 15.6.1-15.6.4, May 1988. A timing generation program allows the sequencer timing to be quickly developed or modified. The sequencer 28 incorporates various pixel and line counters that implement imager read-out functions according to instructions from the system controls, e.g., camera shutter button and the like. The interpolation processor 24 and the post-processor 26 chips include resettable line delays to support signal processing from sensors with up to 768 active photosites per line, making the chips suitable for NTSC, PAL, and CCIR 601 video standards. When applications requiring "higher than video" resolution arise, i.e., requiring a line resolution greater than 768 active photosites, then these "video" custom chips cannot be directly used. Moreover, "higher than video" custom chips devoted to high resolution processing have certain disadvantage since it is difficult to integrate the longer line delays necessary for high resolution processing on a chip of reasonable size.
It is known to provide higher resolution by using two linear sensors with a small overlap between them to scan a large line length (see, e.g., U.S. Pat. Nos. 4,314,281 and 4,692,812). The main concern of such disclosures is the matching of the line outputs at the crossover point, although the '281 patent provides certain initial signal processing in the two separate output channels, in particular a gain adjustment related to the operating characteristics of each array. In U.S. Pat. No. 4,484,349 a parallel pipeline image processor is described in which an image matrix is partitioned so that contiguous segments of the image can be processed simultaneously by two or more adjacent serial neighborhood processors. A processor as described in the '349 patent would not be suitable for the type of imaging system described in the Parulski et al article without the addition of full image storage, which would be very expensive for high resolution image processing. Consequently, the need exists to incorporate the processor chips 24 and 26 of FIG. 1 into a mega-pixel imaging system, particularly one that has the capability of providing vertical interpolation and processing vertically-oriented detail.